The present invention relates to plasma processing conditions used in semiconductor processing, particularly to those used for high density plasma enhanced chemical vapor deposition.
With decreasing transistor gate-lengths and increasing on-chip device densities, the delay at the interconnections has become the determining factor for device speeds at the sub-half micron design level. This is primarily because of increasing lead-lengths and decreasing inter/intra-level dielectric thicknesses, which increases the capacitance and leads to higher RC-time delays. Parasitic capacitance of conductors hurts performance in at least two ways: first, the distributed capacitive load on wiring will slow down the propagation of signals. Secondly, the capacitive coupling between adjacent lines can cause "cross-talk," where a pulse on one line is coupled into an adjacent line. This can lead to unpredictable logic errors. Various solutions have been identified to solve the problem of RC time-delays, such as polymers and organic spin-on materials, but these have yet to gain the level of maturity of CVD silicon dioxide.
The basic HDPCVD process is already well-established in the semiconductor industry. The high density plasma (HDP) source, in combination with a bias RF supply, is normally used for enhanced gap filling and planarization at the smaller geometries and aggressive aspect-ratios for sub 0.5 micrometer technologies. The HDPCVD deposition process involves a simultaneous deposition and etch component.
Parasitic capacitance can be reduced by using insulation with a lower dielectric constant k. Fluorine doping of silicon dioxide deposits using a high-density plasma has been found to lower the dielectric constant from k=4.2 to k=3.0. In order to reduce the dielectric constant to a value between 3.0 and 3.2, a fluorine-containing gas such as CF4, C2F6, or SiF4 is added to the plasma. This results in a high-density fluorinated silica film with a microvoid density usually less than 1%. However, for many applications, the dielectric constant of the silicon dioxide must be further reduced to eliminate the problems of parasitic capacitance and thus, RC time-delays.
Work was previously done by the present inventor to introduce microvoids into silicon; with this disclosure, the use of microvoids is being extended into dielectric insulator materials, in order to lower the dielectric constant.
A previous attempt in this area is discussed in Ceiler et al., "Plasma-Enhanced Chemical Vapor Deposition of Silicon Dioxide Deposited at Low Temperatures", 142 J. Electrochemical Soc. 2067 (1995). This article shows an SiO2 film deposited from 2% silane (in nitrogen) reacted with nitrous oxide. As disclosed therein, this process experienced problems with residual silanol and water being trapped in the film. Since the inclusion of these impurities increases the dielectric constant of the layer, this is counter-productive. Thus, Ceiler appears to teach away from the use of porosity in dielectric layers to decrease permittivity.
Reduced-Dielectric Constant Porous Structures and Methods
In contrast, the process disclosed herein uses a high density plasma chemical vapor deposition (HDPCVD) process to form a micro-porous dielectric layer without --OH bonds. This process uses high ionization densities and does not produce the problems with silanol and water inclusions. The presently preferred embodiment utilizes oxygen and silane as the precursors in the HDPCVD process, and the resulting film contains microvoids (i.e. gas pockets which are less than 100 nanometers) without inclusions of high-dielectric-constant compounds such as silanol and water. The microvoids have a dielectric constant close to k=1.0, and therefore reduce the effective dielectric constant of the silicon dioxide. Control of the deposition process (in particular, the temperature and rate of deposition) allows these microvoids to be formed without residual hydrogen in the film (and consequently without --OH bonds). Additionally, in the disclosed SiH4/O2 oxide deposition process, an oxygen-rich plasma causes an even lower density in the film by promoting a high microvoid concentration.
Advantages of the disclosed methods and structures include:
reduced parasitic capacitance and RC time-delays in interconnect structures; PA1 simple process scheme using the standard chemistry for HDPCVD dielectrics; PA1 doping of silicon dioxide need not be used, eliminating potential reliability issues; and PA1 allows use of CVD silicon dioxide, which is well understood, in smaller geometries.